View MSM51V17805DSL_284741.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2G0129-17-61
Semiconductor MSM51V17805D/DSL
Semiconductor
This version: Mar. 1998 MSM51V17805D/DSL
Pr el im in ar y
2,097,152-Word 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V17805D/DSL is a 2,097,152-word 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V17805D/DSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ double-layer metal CMOS process. The MSM51V17805D/DSL is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. The MSM51V17805DSL (the self-refresh version) is specially designed for lower-power applications.
FEATURES
* 2,097,152-word 8-bit configuration * Single 3.3 V power supply, 0.3 V tolerance * Input : LVTTL compatible, low input capacitance * Output : LVTTL compatible, 3-state * Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version) * Fast page mode with EDO, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * CAS before RAS self-refresh capability (SL version) * Multi-bit test mode capability * Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM51V17805D/DSL-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM51V17805D/DSL-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 84 ns 104 ns 124 ns 360 mW 324 mW 288 mW 1.8 mW/ 0.72 mW (SL version)
MSM51V17805D/DSL-50 50 ns 25 ns 13 ns 13 ns MSM51V17805D/DSL-60 60 ns 30 ns 15 ns 15 ns MSM51V17805D/DSL-70 70 ns 35 ns 20 ns 20 ns
1/17
Semiconductor
PIN CONFIGURATION (TOP VIEW)
VCC 1
A10R 9

28 VSS VCC 1 DQ1 2 27 DQ8 DQ1 2 DQ2 3 DQ3 4 DQ4 5 DQ2 3 DQ3 4 DQ4 5 WE 6 NC 8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE WE 6 NC 8 RAS 7 RAS 7 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS A10R 9 A0 10 A1 11 A2 12 A3 13 VCC 14 28-Pin Plastic SOJ A0 10 A1 11 A2 12 A3 13 VCC 14 Pin Name A0 - A9, A10R RAS CAS DQ1 - DQ8 OE WE VCC VSS Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3 V) Ground (0 V)
MSM51V17805D/DSL
28 VSS 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS
28-Pin Plastic TSOP (K Type)
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
2/17
Semiconductor
MSM51V17805D/DSL
BLOCK DIAGRAM
WE RAS CAS
10
OE
I/O Controller Output Buffers
8
Timing Generator
8
DQ1 - DQ8
Column Address Buffers Internal Address Counter
10 10
Column Decoders
8
Input Buffers
8
A0 - A9
Refresh Control Clock
Sense Amplifiers
8
I/O Selector
8
A10R
1
Row Row Address 11 DecoBuffers ders
Word Drivers
Memory Cells
VCC
On Chip VBB Generator
VSS
3/17
Semiconductor
MSM51V17805D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -0.5 to 4.6 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A9, A10R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ8) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Max. 5 7 7 Unit pF pF pF
4/17
Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Symbol
MSM51V17805D/DSL
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Condition MSM51V17805 MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. VOH IOH = -2.0 mA VOL IOL = 2.0 mA 0 V VI VCC + 0.3 V; ILI All other pins not under test = 0 V DQ disable 0 V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. tRC = 62.5 ms, ICC10 CAS before RAS, tRAS 1 ms RAS 0.2 V, CAS 0.2 V -- 300 -- 300 -- 300 mA 1, 4, 5 -- 100 -- 90 -- 80 mA 1, 3 -- 100 -- 90 -- 80 mA 1, 2 -- 5 -- 5 -- 5 mA 1 -- 100 -- 90 -- 80 mA 1, 2 -10 10 -10 10 -10 10 mA 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh)
ILO
-10
10
-10
10
-10
10
mA
ICC1
-- -- -- --
100 2 0.5 200
-- -- -- --
90 2 0.5 200
-- -- -- --
80 2 0.5 200
mA
1, 2
mA mA
1 1, 5
ICCS
--
300
--
300
--
300
mA
1, 5
Notes : 1. 2. 3. 4. 5.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2 V VIH VCC + 0.3 V, -0.3 V VIL 0.2 V. SL version.
5/17
Semiconductor AC Characteristics (1/2)
MSM51V17805D/DSL
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time
Symbol
MSM51V17805 MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. -- -- -- -- 50 13 25 30 13 -- -- 13 13 13 13 50 32 128 -- 10,000
100,000
Min. 104 135 25 68 -- -- -- -- -- 0 5 0 0 0 0 1 -- -- 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30
Max. -- -- -- -- 60 15 30 35 15 -- -- 15 15 15 15 50 32 128 -- 10,000
100,000
Min. 124 160 30 78 -- -- -- -- -- 0 5 0 0 0 0 1 -- -- 50 70 70 13 13 10 13 45 5 40 5 14 12 0 10 0 13 35
Max. -- -- -- -- 70 20 35 40 20 -- -- 20 20 20 20 50 32 128 -- 10,000
100,000
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tREF tRP tRAS tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL
84 110 20 58 -- -- -- -- -- 0 5 0 0 0 0 1 -- -- 30 50 50 7 7 7 7 35 5 30 5 11 9 0 7 0 7 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 7 3 14 4, 5, 6 4, 5 4, 6 4 4 4
RAS Pulse Width (Fast Page Mode with EDO) tRASP
-- -- -- 10,000 -- -- -- -- 37 25 -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 45 30 -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 50 35 -- -- -- -- --
6/17
Semiconductor AC Characteristics (2/2)
MSM51V17805D/DSL
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3, 12, 13 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS)
Symbol
MSM51V17805MSM51V17805 MSM51V17805 D/DSL-50 D/DSL-60 D/DSL-70 Unit Note Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 10 10 100 110 -50 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 10 10 10 10 100 130 -50 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 14 14 14 11 11 10 10 10 10 9 9 10 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10 10 10 100 90 -50
tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR
WE to RAS Precharge Time (CAS before RAS) tWRP WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) tWTS tWTH tRASS tRPS tCHS
7/17
Semiconductor Notes:
MSM51V17805D/DSL
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 14. Only SL version.
8/17
E2G0102-17-41O Semiconductor MSM51V17805D/DSL
,,, , ,, , ,,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP RAS VIH - VIL - tCRP tCSH tCRP tRCD CAS VIH - VIL - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH - VIL - VIH - VIL - Row Column tRCS tRRH tRCH WE tAA tROH VIH - OE VIL - VOH - tOEA tREZ tRAC tCAC tOEZ tCEZ DQ VOL - Open Valid Data-out tCLZ "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH - VIL -
tCRP
tCRP
tCSH
tRCD
tRSH
VIH - CAS VIL - VIH - VIL - VIH - VIL -
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
Row
Column
tWCS
WE
tWCH tWP
tCWL
tRWL
OE
VIH - VIL - VIH -
tDS
tDH
DQ
VIL -
Valid Data-in
Open
"H" or "L"
9/17
,,,
Semiconductor MSM51V17805D/DSL Read Modify Write Cycle
tRWC tRAS tRP VIH - RAS VIL - tCSH tCRP tCRP tRCD tRSH CAS VIH - VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L"
10/17
Semiconductor
Fast Page Mode Read Cycle (Part-1)
Address
Fast Page Mode Read Cycle (Part-2)
Address
, ,,, , ,
MSM51V17805D/DSL
tRASP tRP RAS VIH - VIL - tRHCP tCRP tRCD tHPC tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column Column tRCS tRRH WE tCHO tOCH tRAC tAA tOEP OE tAA tAA tOEP tOEA tCAC tCPA tDOH tCAC tOEA tOEA tOEZ tCAC tOEZ tREZ DQ VOH - VOL - tCLZ
Valid Data-out
Valid Data-out Valid* Data-out Valid* Data-out
* : Same Data,
"H" or "L"
tRASP
tRP
RAS
VIH - VIL -
tRHCP
tCRP
tCRP
tHPC
tRCD
tCP
tCP
CAS
VIH - VIL -
tCAS
tCAS
tCAS
tRAD
tASR
tRAH
tCSH tASC tCAH Column
tASC
tCAH
tASC
tCAH
VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
Column
tRCS
tRCS
WE
tRAC tAA
tRCH
tWPE
tAA
tAA
OE
tCPA
tOEA tCAC
tWEZ
tCAC
tCAC tDOH
tCEZ
DQ
VOH - VOL -
tCLZ
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
11/17
,, , , ,
Semiconductor MSM51V17805D/DSL Fast Page Mode Write Cycle (Early Write)
VIH - VIL - tRASP tRP RAS tCRP tRCD tHPC tHPC tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Address VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH WE OE tDS tDH tDS tDH tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in "H" or "L"
Fast Page Mode Read Modify Write Cycle
tRASP
RAS
VIH - VIL -
tRWD
tCRP
tRCD
tCP
CAS
VIH - VIL -
tRAD
tCWD
tASR
tRAH tASC
tHPRWC
tCPWD tASC
tCAH
tCWL
tCPA tCAH
tRWL
Address
VIH - VIL -
Row
Column
Column
tRCS
tAWD
tRCS
tCWD
WE
VIH - VIL -
tRAC
tAWD
tAA
tDS tWP
tAA
tDS
tWP
OE
VIH - VIL -
tOEA
tOED
tOEH tDH
tOEA
tOED
tOEH tDH
tCAC
tOEZ
tCAC
tOEZ
DQ
VI/OH - VI/OL -
Valid Data-out
Valid Data-in
Valid Data-out
Valid Data-in
tCLZ
tCLZ
"H" or "L"
12/17
Semiconductor RAS-Only Refresh Cycle
t RC tRAS RAS V IH - V IL - tCRP CAS V IH - V IL - tASR Address V IH - V IL - tCEZ DQ V OH - V OL - Open Row tRAH
MSM51V17805D/DSL
tRP
tRPC
Note: WE, OE = "H" or "L"
"H" or "L"
CAS before RAS Refresh Cycle
tRC t RP RAS VIH - VIL - tRPC tCP CAS VIH - VIL - tWRP WE VIH - VIL - t CEZ DQ VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L" tWRH tWRP tCSR tCHR tRAS t RPC tRP
13/17
Semiconductor
Hidden Refresh Read Cycle
,,, ,, ,, ,
MSM51V17805D/DSL
tRC tRAS tRP tRC tRAS tRP RAS VIH - VIL - tCRP tRCD tRSH tCHR CAS VIH - VIL - VIH - VIL - VIH - VIL - tASR tRAH tRAD tASC tCAH Address Row Column tRCS tRAL tRRH WE tAA tROH OE VIH - VIL - tOEA tRAC tCAC tCLZ tCEZ tOEZ tREZ DQ VOH - VOL - Open Valid Data-out "H" or "L"
Hidden Refresh Write Cycle
tRC tRAS
tRP
tRC tRAS
tRP
RAS
VIH - VIL - VIH - VIL -
tCRP
tRCD
tRSH
tCHR
CAS
tASR
tRAH
tRAD tASC
tCAH
tRAL
Address
VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
tWCS
tRWL tWCH
WE
tWP
OE
tDS
tDH
DQ
Valid Data-in "H" or "L"
14/17
Semiconductor CAS before RAS Self-Refresh Cycle
tRP RAS VIH - VIL - VIH - VIL - VIH - VIL - VOH - VOL - t RPC tCP tRC tRAS
MSM51V17805D/DSL
tCSR
tCHR
CAS
tWTS
tWTH
WE DQ
t OFF Open Note: OE, Address = "H" or "L" Only SL version "H" or "L"
Test Mode Initiate Cycle
RAS
CAS
WE
DQ
,
tRC tRP tRAS VIH - VIL - tRPC tCP tCSR tCHR VIH - VIL - tWTS tWTH VIH - VIL - tOFF VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L"
15/17
Semiconductor
MSM51V17805D/DSL
PACKAGE DIMENSIONS
(Unit : mm)
SOJ28-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
16/17
Semiconductor
MSM51V17805D/DSL
(Unit : mm)
TSOPII28-P-400-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.51 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
17/17

▲Up To Search▲

Price & Availability of MSM51V17805DSL

	To Download MSM51V17805DSL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .